1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and in particular, to an output enable signal generating circuit and method for a semiconductor memory apparatus.
2. Related Art
In general, semiconductor memory apparatuses output data after CAS (Column Address Strobe) latency, which is based on a clock transmitted from a DLL (Delay Locked Loop) circuit and is specified in a number of clock cycles. In order to buffer output data, a conventional semiconductor apparatus is required to set a buffering interval for the output data. In order to set a buffering interval for the output data, a conventional semiconductor memory apparatus is provided with an output enable signal generating circuit. If receiving a read command, the output enable signal generating circuit generates an output enable signal on the basis of CAS latency information and a DLL clock.
A conventional semiconductor memory apparatus generally uses a DLL circuit to generate DLL clock signals and occasionally use a DLL off mode under specific conditions. For example, when an apparatus for testing a semiconductor memory apparatus operates at a relatively low frequency, or when it is required to significantly reduce power consumption is called for in the semiconductor apparatus, the DLL off mode is used. Whether to use the DLL off mode is determined according to whether a DLL on mode signal is enabled.
Referring to FIG. 1, a conventional semiconductor memory apparatus includes a read command generator 1, a DLL circuit 2, an output enable signal generating circuit 3, a core circuit 4, and a data output buffer 5.
The read command generator 1 generates a read command ‘RD_cmd’ in response to an external clock signal ‘clk_ext’ and an external read command ‘RD_cmdext’. The DLL circuit 2 receives the external clock signal ‘clk_ext’ and generates a DLL clock signal ‘clk_dll’. The output enable signal generating circuit 3 receives a reset signal ‘rst’, a CAS latency signal ‘CL’, a DLL on mode signal ‘donmd’, the read command ‘RD_cmd’, the DLL clock signal ‘clk_dll’, and the external clock signal ‘clk_ext’, and generates an output enable signal ‘outen’. The core circuit 4 ouptuts a GIO data signal ‘d_gio’ in response to the external read command ‘RD_cmdext’. The data output buffer 5 outputs an output data signal ‘d_out’ in response to the output enable signal ‘outen’ and the GIO data signal ‘d_gio’.
Referring to FIG. 2, the output enable signal generating circuit 3 includes a CAS latency delay unit 31, a data output delay control unit 32, an output enable signal output unit 33, a DLL off output enable signal generating unit 34, and an output enable multiplex unit 35.
The CAS latency delay unit 31 generates a CAS latency delay signal ‘CL_dly’ in response to the CAS latency signal ‘CL’, the external clock signal ‘clk_ext’, and the reset signal ‘rst’. The data output delay control unit 32 generates an output enable delay signal ‘oedly’ in response to the reset signal ‘rst’ and the CAS latency delay signal ‘CL_dly’. The output enable signal output unit 33 generates a DLL on output enable signal ‘outen_don’ in response to the read command ‘RD_cmd’, the output enable delay signal ‘oedly’, the DLL clock signal ‘clk_dll’, and the DLL on mode signal ‘donmd’.
The DLL off output enable signal generating unit 34 generates a DLL off output enable signal ‘outen_doff’ in response to the read command ‘RD_cmd’, the DLL clock signal ‘clk_dll’, and the DLL on mode signal ‘donmd’. The output enable multiplex unit 35 outputs the DLL on output enable signal ‘outen_don’ or the DLL off output enable signal ‘outen_doff’ as an output enable signal ‘outen’.
The CAS latency delay unit 31 may be implemented as a shift register that shifts the CAS latency signal ‘CL’ in sync with the external clock signal ‘clk_ext’.
Referring to FIG. 3, the data output delay unit 32 includes a replica delay unit REPDL, a first inverter IV1, a second inverter IV2, a first NAND gate ND1, and a NOR gate NR.
The replica delay unit REPDL receives the reset signal ‘rst’. The first inverter IV1 receives an output signal of the replica delay unit REPDL. The first NAND gate ND1 receives the reset signal ‘rst’ and an output signal of the first inverter IV1. The second inverter IV2 receives an output signal of the first NAND gate ND1. The NOR gate NR receives an output signal of the second inverter IV2 and the CAS latency delay signal ‘CL_dly’, and outputs the output enable delay signal ‘oedly’.
The reset signal ‘rst’ is often implemented as a low enable signal.
Referring to FIG. 4, the DLL off output enable signal generating unit 34 includes a delay unit DLY, a plurality of second NAND gates ND2<1:n-1>, and a plurality of flip-flops FF<1:n-1>.
The delay unit DLY delays the read command ‘RD_cmd’ and outputs the delayed read command ‘RD_cmddly’.
The CAS latency signal is often implemented as a plurality of signals ‘CL<2:n>’, which are enabled according to the length of CAS latency.
The plurality of second NAND gates ND2<1:n-1> each receive the delayed read command ‘RD_cmddly’ and one of the plurality of CAS latency signals ‘CL<2:n>’ that is pre-assigned thereto. The plurality of flip-flops FF<1:n-1> each receive the reset signal ‘rs’, the DLL clock signal ‘clk_dll’, an output signal of one of the plurality of second NAND gates ND2<1:n-1> pre-assigned thereto, and an output signal of the preceding flip-flop. The (n-1)th flip-flop FF<n-1> outputs the DLL off output enable signal ‘outen_doff’.
In a DLL on mode, the phase of the internal clock signal (that is, the DLL clock signal) is earlier than the phase of the external clock signal. In contrast, in a DLL off mode, the phase of the internal clock signal is later than the phase of the external clock signal. Therefore, the timing from when the read command is input until data is output is larger in the DLL off mode, as compared to the DLL on mode. In the case where the CAS latency is 4, data should be output four cycles of the external clock signal after the read command is input. Thus, in the DLL on mode, the output enable signal generating circuit generates an output enable signal having an enable interval of four cycles of the external clock signal, corresponding to the four cock cycles that follow reception of the read command.
In contrast, in the DLL off mode, the output enable signal generating circuit generates an output enable signal having an enable interval that begins four cycles of the external clock signal after reception of the read command.
In order to generate output enable signals having different enable timing in the DLL on mode and in the DLL off mode, a conventional output enable signal generating circuit for a semiconductor memory apparatus often includes a circuit for generating an output enable signal in the DLL on mode and a circuit for generating an output enable signal in the DLL off mode. Accordingly, the area occupied by the output enable signal generating circuit is relatively large, which reduces the area efficiency of the apparatus.
Increased integration is critical for many conventional semiconductor apparatus. Accordingly, the reduced area efficiency that results from supporting both a DLL on mode and a DLL off mode has a significant negative impact.